#name: SME extension (ST1x instructions)
#as: -march=armv8-a+sme
#objdump: -dr

.*:     file format .*

Disassembly of section \.text:

0+ <.*>:
   0:	e03f0000 	st1b	{za0h.b\[w12, 0\]}, p0, \[x0, xzr\]
   4:	e03f03e0 	st1b	{za0h.b\[w12, 0\]}, p0, \[sp, xzr\]
   8:	e02003e0 	st1b	{za0h.b\[w12, 0\]}, p0, \[sp, x0\]
   c:	e03f7e2f 	st1b	{za0h.b\[w15, 15\]}, p7, \[x17, xzr\]
  10:	e03f7fef 	st1b	{za0h.b\[w15, 15\]}, p7, \[sp, xzr\]
  14:	e0317fef 	st1b	{za0h.b\[w15, 15\]}, p7, \[sp, x17\]
  18:	e07f0000 	st1h	{za0h.h\[w12, 0\]}, p0, \[x0, xzr, lsl #1\]
  1c:	e07f03e0 	st1h	{za0h.h\[w12, 0\]}, p0, \[sp, xzr, lsl #1\]
  20:	e0600000 	st1h	{za0h.h\[w12, 0\]}, p0, \[x0, x0, lsl #1\]
  24:	e06003e0 	st1h	{za0h.h\[w12, 0\]}, p0, \[sp, x0, lsl #1\]
  28:	e07f7e2f 	st1h	{za1h.h\[w15, 7\]}, p7, \[x17, xzr, lsl #1\]
  2c:	e07f7fef 	st1h	{za1h.h\[w15, 7\]}, p7, \[sp, xzr, lsl #1\]
  30:	e0717c0f 	st1h	{za1h.h\[w15, 7\]}, p7, \[x0, x17, lsl #1\]
  34:	e0717fef 	st1h	{za1h.h\[w15, 7\]}, p7, \[sp, x17, lsl #1\]
  38:	e0bf0000 	st1w	{za0h.s\[w12, 0\]}, p0, \[x0, xzr, lsl #2\]
  3c:	e0bf03e0 	st1w	{za0h.s\[w12, 0\]}, p0, \[sp, xzr, lsl #2\]
  40:	e0a00000 	st1w	{za0h.s\[w12, 0\]}, p0, \[x0, x0, lsl #2\]
  44:	e0a003e0 	st1w	{za0h.s\[w12, 0\]}, p0, \[sp, x0, lsl #2\]
  48:	e0bf7e2f 	st1w	{za3h.s\[w15, 3\]}, p7, \[x17, xzr, lsl #2\]
  4c:	e0bf7fef 	st1w	{za3h.s\[w15, 3\]}, p7, \[sp, xzr, lsl #2\]
  50:	e0b17c0f 	st1w	{za3h.s\[w15, 3\]}, p7, \[x0, x17, lsl #2\]
  54:	e0b17fef 	st1w	{za3h.s\[w15, 3\]}, p7, \[sp, x17, lsl #2\]
  58:	e0ff0000 	st1d	{za0h.d\[w12, 0\]}, p0, \[x0, xzr, lsl #3\]
  5c:	e0ff03e0 	st1d	{za0h.d\[w12, 0\]}, p0, \[sp, xzr, lsl #3\]
  60:	e0e00000 	st1d	{za0h.d\[w12, 0\]}, p0, \[x0, x0, lsl #3\]
  64:	e0e003e0 	st1d	{za0h.d\[w12, 0\]}, p0, \[sp, x0, lsl #3\]
  68:	e0ff7e2f 	st1d	{za7h.d\[w15, 1\]}, p7, \[x17, xzr, lsl #3\]
  6c:	e0ff7fef 	st1d	{za7h.d\[w15, 1\]}, p7, \[sp, xzr, lsl #3\]
  70:	e0f17c0f 	st1d	{za7h.d\[w15, 1\]}, p7, \[x0, x17, lsl #3\]
  74:	e0f17fef 	st1d	{za7h.d\[w15, 1\]}, p7, \[sp, x17, lsl #3\]
  78:	e1ff0000 	st1q	{za0h.q\[w12, 0\]}, p0, \[x0, xzr, lsl #4\]
  7c:	e1ff03e0 	st1q	{za0h.q\[w12, 0\]}, p0, \[sp, xzr, lsl #4\]
  80:	e1e00000 	st1q	{za0h.q\[w12, 0\]}, p0, \[x0, x0, lsl #4\]
  84:	e1e003e0 	st1q	{za0h.q\[w12, 0\]}, p0, \[sp, x0, lsl #4\]
  88:	e1ff7e2f 	st1q	{za15h.q\[w15, 0\]}, p7, \[x17, xzr, lsl #4\]
  8c:	e1ff7fef 	st1q	{za15h.q\[w15, 0\]}, p7, \[sp, xzr, lsl #4\]
  90:	e1f17c0f 	st1q	{za15h.q\[w15, 0\]}, p7, \[x0, x17, lsl #4\]
  94:	e1f17fef 	st1q	{za15h.q\[w15, 0\]}, p7, \[sp, x17, lsl #4\]
  98:	e03f8000 	st1b	{za0v.b\[w12, 0\]}, p0, \[x0, xzr\]
  9c:	e03f83e0 	st1b	{za0v.b\[w12, 0\]}, p0, \[sp, xzr\]
  a0:	e02083e0 	st1b	{za0v.b\[w12, 0\]}, p0, \[sp, x0\]
  a4:	e03ffe2f 	st1b	{za0v.b\[w15, 15\]}, p7, \[x17, xzr\]
  a8:	e03fffef 	st1b	{za0v.b\[w15, 15\]}, p7, \[sp, xzr\]
  ac:	e031ffef 	st1b	{za0v.b\[w15, 15\]}, p7, \[sp, x17\]
  b0:	e07f8000 	st1h	{za0v.h\[w12, 0\]}, p0, \[x0, xzr, lsl #1\]
  b4:	e07f83e0 	st1h	{za0v.h\[w12, 0\]}, p0, \[sp, xzr, lsl #1\]
  b8:	e0608000 	st1h	{za0v.h\[w12, 0\]}, p0, \[x0, x0, lsl #1\]
  bc:	e06083e0 	st1h	{za0v.h\[w12, 0\]}, p0, \[sp, x0, lsl #1\]
  c0:	e07ffe2f 	st1h	{za1v.h\[w15, 7\]}, p7, \[x17, xzr, lsl #1\]
  c4:	e07fffef 	st1h	{za1v.h\[w15, 7\]}, p7, \[sp, xzr, lsl #1\]
  c8:	e071fc0f 	st1h	{za1v.h\[w15, 7\]}, p7, \[x0, x17, lsl #1\]
  cc:	e071ffef 	st1h	{za1v.h\[w15, 7\]}, p7, \[sp, x17, lsl #1\]
  d0:	e0bf8000 	st1w	{za0v.s\[w12, 0\]}, p0, \[x0, xzr, lsl #2\]
  d4:	e0bf83e0 	st1w	{za0v.s\[w12, 0\]}, p0, \[sp, xzr, lsl #2\]
  d8:	e0a08000 	st1w	{za0v.s\[w12, 0\]}, p0, \[x0, x0, lsl #2\]
  dc:	e0a083e0 	st1w	{za0v.s\[w12, 0\]}, p0, \[sp, x0, lsl #2\]
  e0:	e0bffe2f 	st1w	{za3v.s\[w15, 3\]}, p7, \[x17, xzr, lsl #2\]
  e4:	e0bfffef 	st1w	{za3v.s\[w15, 3\]}, p7, \[sp, xzr, lsl #2\]
  e8:	e0b1fc0f 	st1w	{za3v.s\[w15, 3\]}, p7, \[x0, x17, lsl #2\]
  ec:	e0b1ffef 	st1w	{za3v.s\[w15, 3\]}, p7, \[sp, x17, lsl #2\]
  f0:	e0ff8000 	st1d	{za0v.d\[w12, 0\]}, p0, \[x0, xzr, lsl #3\]
  f4:	e0ff83e0 	st1d	{za0v.d\[w12, 0\]}, p0, \[sp, xzr, lsl #3\]
  f8:	e0e08000 	st1d	{za0v.d\[w12, 0\]}, p0, \[x0, x0, lsl #3\]
  fc:	e0e083e0 	st1d	{za0v.d\[w12, 0\]}, p0, \[sp, x0, lsl #3\]
 100:	e0fffe2f 	st1d	{za7v.d\[w15, 1\]}, p7, \[x17, xzr, lsl #3\]
 104:	e0ffffef 	st1d	{za7v.d\[w15, 1\]}, p7, \[sp, xzr, lsl #3\]
 108:	e0f1fc0f 	st1d	{za7v.d\[w15, 1\]}, p7, \[x0, x17, lsl #3\]
 10c:	e0f1ffef 	st1d	{za7v.d\[w15, 1\]}, p7, \[sp, x17, lsl #3\]
 110:	e1ff8000 	st1q	{za0v.q\[w12, 0\]}, p0, \[x0, xzr, lsl #4\]
 114:	e1ff83e0 	st1q	{za0v.q\[w12, 0\]}, p0, \[sp, xzr, lsl #4\]
 118:	e1e08000 	st1q	{za0v.q\[w12, 0\]}, p0, \[x0, x0, lsl #4\]
 11c:	e1e083e0 	st1q	{za0v.q\[w12, 0\]}, p0, \[sp, x0, lsl #4\]
 120:	e1fffe2f 	st1q	{za15v.q\[w15, 0\]}, p7, \[x17, xzr, lsl #4\]
 124:	e1ffffef 	st1q	{za15v.q\[w15, 0\]}, p7, \[sp, xzr, lsl #4\]
 128:	e1f1fc0f 	st1q	{za15v.q\[w15, 0\]}, p7, \[x0, x17, lsl #4\]
 12c:	e1f1ffef 	st1q	{za15v.q\[w15, 0\]}, p7, \[sp, x17, lsl #4\]
